1. Field of the Invention
The invention relates to the field of frame buffers for video displays and more particular, to addressing mechanisms for frame buffers.
2. Prior Art
Video random-access memories (VRAMs) have become commercially available in recent years for use with video displays. These devices include a memory array for storing pixel data and a shift register both formed on the same substrate. A row address is used to transfer data to the shift register. A column address is then used to identify a starting location in the shift register from which data is read out. Shift register operations can occur asynchronously with array accesses. Typically, the data is shifted out of the shift register at a much faster rate than that associated with dynamic RAM accessing.
In many applications, there is an integer number of scan lines displayed per row line in the memory. That is, a shift integer is not emptied midway in a scan line. There are timing and other problems if this correlation is not maintained.
The present invention provides circuitry for addressing the VRAMs while allowing a non-integer or integer number of scan lines per row of video memory. Among the features provided by the present invention is a lookahead mechanism used to initiate a memory cycle before the shift register is emptied. This permits the shift register to become empty in the middle of a scan line and to be reloaded in time to continue the scan.